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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-06-25 10:39:58 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-06-25 10:39:58 +0200 |
| commit | ed1d98d801dfb6384d0f2fff45ce1ebf884944ca (patch) | |
| tree | 5a9487c67b75606d3a723b7acb9eda8da200c871 /drivers/ddr/fsl/ctrl_regs.c | |
| parent | 754466ac95e92ebf40e25c6af6f13ab9b4d7c87b (diff) | |
| parent | ba9b42c81b0734d53edfbb1fe4a6ded7de78c5ab (diff) | |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
Diffstat (limited to 'drivers/ddr/fsl/ctrl_regs.c')
| -rw-r--r-- | drivers/ddr/fsl/ctrl_regs.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 78e82bba3d4..dcf6287f663 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -2304,5 +2304,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, ddr->debug[2] = 0x00000400; ddr->debug[4] = 0xff800000; #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004508 + if ((ip_rev >= 0x40000) && (ip_rev < 0x40400)) + ddr->debug[2] |= 0x00000200; /* set bit 22 */ +#endif + return check_fsl_memctl_config_regs(ddr); } |