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| author | Simon Glass <sjg@chromium.org> | 2024-08-27 19:44:26 -0600 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2024-10-18 14:10:21 -0600 |
| commit | 7c0f70b65b7c6ab0c09f87932615c65142542ed5 (patch) | |
| tree | 80b38c1484bfb731e715c71dbcd3f376819f0073 /drivers/ddr/fsl/ddr1_dimm_params.c | |
| parent | 3b2e4f542e3ea5d116d5830f4eef9be97d872312 (diff) | |
x86: Avoid timer-clock overflow
When the clock speed is above about 4GHz, e.g. on modern PC hardware,
the timer overflows, resulting in a much lower frequency than expected.
Deal with this by capping the clock speed.
It would be possible to move to a 64-bit value for the clock, but that
is a pain to deal with. A better approach might be to express the clock
in MHz but that is left for later consideration.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/ddr/fsl/ddr1_dimm_params.c')
0 files changed, 0 insertions, 0 deletions