diff options
| author | Tien Fong Chee <tien.fong.chee@intel.com> | 2024-08-08 16:47:39 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-02-25 10:53:56 -0600 |
| commit | 9bb68bff4efaff541a6d19f11f14d269f5f89a19 (patch) | |
| tree | 907454c7d04a3835b451118755479b56c2661d75 /drivers/ddr/fsl/fsl_ddr_gen4.c | |
| parent | 7d2f2883dcda6f2145e01ba7b5289ceb5d1e81e1 (diff) | |
arm: socfpga: agilex5: Enable cache flush for system memory cache in CCU
set/way instructions "dc cisw" which is used by the "dcache flush" command
only flushing CPU data caches from L1 -> L2 -> L3 to system memory cache in
cache coherency unit, hence this patch enables data flush from system
memory cache of CCU into DDR memory.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Diffstat (limited to 'drivers/ddr/fsl/fsl_ddr_gen4.c')
0 files changed, 0 insertions, 0 deletions