diff options
author | Tom Rini <trini@konsulko.com> | 2021-11-11 09:04:20 -0500 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2021-11-11 09:04:20 -0500 |
commit | 1e72ad6b387c599f477f83cda67ab525c089a9b0 (patch) | |
tree | e9902c9fb94534a8c98d880db36a74a8ec17e173 /drivers/ddr/fsl/lc_common_dimm_params.c | |
parent | 166a77b34b30f64f7b12a3016b0bba49d568c52e (diff) | |
parent | 99e1fa89f1a6ce13787af34cbd933c846bc7e93a (diff) |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- device-tree sync-up with Linux for ls1028a
- fixes/update in fsl-ddr driver, fsl-validate, lx2162a, fsl-mc,
spintable code, configs, qspi node, pci
- enable EFI_SET_TIME support in sl28
- powerpc: Drop -mstring
Diffstat (limited to 'drivers/ddr/fsl/lc_common_dimm_params.c')
-rw-r--r-- | drivers/ddr/fsl/lc_common_dimm_params.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c index d299d763db1..d738ae3a7c6 100644 --- a/drivers/ddr/fsl/lc_common_dimm_params.c +++ b/drivers/ddr/fsl/lc_common_dimm_params.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright 2008-2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP Semiconductor + * Copyright 2017-2021 NXP Semiconductor */ #include <common.h> @@ -23,7 +23,7 @@ compute_cas_latency(const unsigned int ctrl_num, unsigned int caslat_actual; unsigned int retry = 16; unsigned int tmp = ~0; - const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); + unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); #ifdef CONFIG_SYS_FSL_DDR3 const unsigned int taamax = 20000; #else @@ -37,6 +37,12 @@ compute_cas_latency(const unsigned int ctrl_num, } common_caslat = tmp; + if (!mclk_ps) { + printf("DDR clock (MCLK cycle was 0 ps), So setting it to slowest DIMM(s) (tCKmin %u ps).\n", + outpdimm->tckmin_x_ps); + mclk_ps = outpdimm->tckmin_x_ps; + } + /* validate if the memory clk is in the range of dimms */ if (mclk_ps < outpdimm->tckmin_x_ps) { printf("DDR clock (MCLK cycle %u ps) is faster than " |