diff options
| author | Tom Rini <trini@konsulko.com> | 2022-10-28 20:27:13 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-11-10 10:08:55 -0500 |
| commit | 6cc04547cb3bbd3a3d78947f200acbae19e3c67f (patch) | |
| tree | 518a634e223bfb02d08ca359331a4ec08c20513c /drivers/ddr/fsl/main.c | |
| parent | 5155207ae1a0797a99c0a5f4e99741960ff04697 (diff) | |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/ddr/fsl/main.c')
| -rw-r--r-- | drivers/ddr/fsl/main.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index ed3313a5315..fcff223b4f0 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -21,18 +21,18 @@ #include <asm/bitops.h> /* - * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view + * CFG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for * all Power SoCs. But it could be different for ARM SoCs. For example, * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of * 0x00_8000_0000 ~ 0x00_ffff_ffff * 0x80_8000_0000 ~ 0xff_ffff_ffff */ -#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY +#ifndef CFG_SYS_FSL_DDR_SDRAM_BASE_PHY #ifdef CONFIG_MPC83xx -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE #else -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE #endif #endif @@ -898,7 +898,7 @@ phys_size_t fsl_ddr_sdram(void) /* Reset info structure. */ memset(&info, 0, sizeof(fsl_ddr_info_t)); - info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; + info.mem_base = CFG_SYS_FSL_DDR_SDRAM_BASE_PHY; info.first_ctrl = 0; info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS; info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR; @@ -946,7 +946,7 @@ fsl_ddr_sdram_size(void) unsigned long long total_memory = 0; memset(&info, 0 , sizeof(fsl_ddr_info_t)); - info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; + info.mem_base = CFG_SYS_FSL_DDR_SDRAM_BASE_PHY; info.first_ctrl = 0; info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS; info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR; |