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| author | Christian Marangi <ansuelsmth@gmail.com> | 2024-08-02 15:53:04 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-08-19 16:13:13 -0600 |
| commit | a3cc4a4810c3e195ccdb75e148a41e4668cbb36c (patch) | |
| tree | cca7887b10176f936fdd457a47b5648fad2f06b9 /drivers/ddr/fsl/main.c | |
| parent | 99d3da81bdd98c602d6d2e6585e3e6553caec7b8 (diff) | |
clk: mediatek: mt7981: fix wrong mux width for pwm2 and pwm1 clock
Fix wrong mux width for pwm2 and pwm1. Upstream have width 1 but U-Boot
have width set to 2. Change the value to follow upstream implementation.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Diffstat (limited to 'drivers/ddr/fsl/main.c')
0 files changed, 0 insertions, 0 deletions