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| author | Tom Rini <trini@konsulko.com> | 2023-01-09 11:30:08 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-01-09 11:30:08 -0500 |
| commit | cebdfc22da6eb81793b616e855bc4d6d89c1c7a6 (patch) | |
| tree | 44eaafcbe4866712d361304882e7d56ca0ef1682 /drivers/ddr/fsl/main.c | |
| parent | 62e2ad1ceafbfdf2c44d3dc1b6efc81e768a96b9 (diff) | |
| parent | fe33066d246462551f385f204690a11018336ac8 (diff) | |
Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'drivers/ddr/fsl/main.c')
| -rw-r--r-- | drivers/ddr/fsl/main.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index fcff223b4f0..cd332718b64 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -22,7 +22,7 @@ /* * CFG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view - * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for + * of DDR controllers. It is the same as CFG_SYS_DDR_SDRAM_BASE for * all Power SoCs. But it could be different for ARM SoCs. For example, * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of * 0x00_8000_0000 ~ 0x00_ffff_ffff @@ -30,9 +30,9 @@ */ #ifndef CFG_SYS_FSL_DDR_SDRAM_BASE_PHY #ifdef CONFIG_MPC83xx -#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_SDRAM_BASE #else -#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_DDR_SDRAM_BASE #endif #endif |