diff options
| author | Tom Rini <trini@konsulko.com> | 2022-12-05 21:04:24 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-12-05 21:04:24 -0500 |
| commit | d2ad92927ea91ab8cece92a308350602c594dd3e (patch) | |
| tree | 23ec41dc6f0aff10b800c69396a32ac5ac926817 /drivers/ddr/fsl/main.c | |
| parent | 1c470f32f74248ff4aa145bf033fb6524dc7fc2e (diff) | |
| parent | 7102d324f6b41741ee74587d43d77b302b1bbd96 (diff) | |
Merge branch '2022-12-05-Kconfig-migrations-and-renames' into next
- First batch of the patches that end up with
scripts/config_whitelist.tx being empty. Mostly migrations and a
little bit of code removal and CFG renaming.
Diffstat (limited to 'drivers/ddr/fsl/main.c')
| -rw-r--r-- | drivers/ddr/fsl/main.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index fcff223b4f0..cd332718b64 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -22,7 +22,7 @@ /* * CFG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view - * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for + * of DDR controllers. It is the same as CFG_SYS_DDR_SDRAM_BASE for * all Power SoCs. But it could be different for ARM SoCs. For example, * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of * 0x00_8000_0000 ~ 0x00_ffff_ffff @@ -30,9 +30,9 @@ */ #ifndef CFG_SYS_FSL_DDR_SDRAM_BASE_PHY #ifdef CONFIG_MPC83xx -#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_SDRAM_BASE #else -#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_DDR_SDRAM_BASE #endif #endif |