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| author | Tom Rini <trini@konsulko.com> | 2021-08-31 17:52:28 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-08-31 17:55:32 -0400 |
| commit | df6cf3d809fe543651e6bdf133baaa8b9841fe0f (patch) | |
| tree | a884597e97578cb074adc33d3dd961d6675c9879 /drivers/ddr/fsl | |
| parent | a85a8e63c5cf8ccb3905eb5982bf8bdcb2978557 (diff) | |
| parent | b4c2c151b14b59a2403675526adf666710cade67 (diff) | |
Merge branch '2021-08-31-kconfig-migrations-part2' into next
- Further CONFIG to Kconfig migrations
- Some DDR related symbols
- CONFIG_SYS_LOAD_ADDR moved, loadaddr always set in environment now.
- Finish MX7D, convert IMX_CONFIG
- Some RAMBOOT related options
- L1 cache size converted and named consistently for all arches. A
further follow-up to rename things for even better clarity is welcome.
- CONFIG_SKIP_LOWLEVEL_INIT, CONFIG_SYS_MALLOC_LEN
Diffstat (limited to 'drivers/ddr/fsl')
| -rw-r--r-- | drivers/ddr/fsl/Kconfig | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index 8246f627982..fe3d6fc9700 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -10,6 +10,8 @@ config SYS_FSL_MMDC help Select Freescale Multi Mode DDR controller (MMDC). +if SYS_FSL_DDR || SYS_FSL_MMDC + config SYS_FSL_DDR_BE bool help @@ -116,28 +118,51 @@ choice config SYS_FSL_DDR4 bool "Freescale DDR4 controller" depends on SYS_FSL_HAS_DDR4 + imply DDR_SPD select SYS_FSL_DDRC_GEN4 config SYS_FSL_DDR3 bool "Freescale DDR3 controller" depends on SYS_FSL_HAS_DDR3 + imply DDR_SPD select SYS_FSL_DDRC_GEN3 if PPC select SYS_FSL_DDRC_ARM_GEN3 if ARM config SYS_FSL_DDR2 bool "Freescale DDR2 controller" depends on SYS_FSL_HAS_DDR2 + imply DDR_SPD select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3) config SYS_FSL_DDR1 bool "Freescale DDR1 controller" depends on SYS_FSL_HAS_DDR1 + imply DDR_SPD select SYS_FSL_DDRC_GEN1 endchoice endmenu +config FSL_DMA + def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER + +config DDR_ECC + bool "ECC DDR memory support" + +config DDR_ECC_CMD + bool "Access the ECC features of the memory controller" + depends on DDR_ECC && MPC83xx + default y + +config ECC_INIT_VIA_DDRCONTROLLER + bool "DDR Memory controller initializes memory." + help + Use the DDR controller to auto initialize memory. If not enabled, + the DMA controller is responsible for doing this. + +endif + config SYS_FSL_ERRATUM_A008378 bool |