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| author | Christian Marangi <ansuelsmth@gmail.com> | 2024-08-02 15:45:05 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-08-19 16:12:51 -0600 |
| commit | 5c15548f7dc2f2e3c0a487c3e96a2e862c99421a (patch) | |
| tree | c163177a06c363df5bde69e769e1fa282109d33d /drivers/ddr/imx/imx8m/ddr_init.c | |
| parent | 57f7ddd1b2350a3964827f78abb29a11bc87947f (diff) | |
clk: mediatek: mt7623: remap peri clock ID and add MUX
Upstream kernel linux makes use of peri clock MUX to setup UART.
Add definition for these and add remap table as in the upstream clock ID
order gates are before MUX but we require MUX first and then clocks in
our downstream driver.
Convert the peri clk tree to MUX + GATE implementation.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Diffstat (limited to 'drivers/ddr/imx/imx8m/ddr_init.c')
0 files changed, 0 insertions, 0 deletions