clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching

Do not cache the single CPG MODE register bit 12, instead cache the
entire register value, and only pick the matching bit from the cached
value when core clock of type MDSEL or PE are used. Both MDSEL and PE
clock type currently define .offset field as 12 on Gen3, which means
this code will use bit 12 on Gen3 again, however there are additional
clock on Gen4 which use different bits, and having this flexibility
in place now will be useful when adding Gen4.

No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

0 files changed, 0 insertions, 0 deletions