diff options
| author | Frieder Schrempf <frieder.schrempf@kontron.de> | 2019-12-11 10:01:19 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2020-01-07 10:26:57 +0100 |
| commit | 83083febf55679ee0fc68ba55e9af43add277b58 (patch) | |
| tree | b2495a3ed95c2ec411c67de34cccb125f4dbd2ba /drivers/ddr/imx/imx8m/ddrphy_train.c | |
| parent | 162c72c80445636ec73f8833b9e91f0128d21b8f (diff) | |
ddr: imx8m: Return error values from LPDDR4 training
In cases when the same SPL should run on boards with i.MX8MM, that
differ in DDR configuration, it is necessary to try different
parameters and check if the training done by the firmware suceeds or
not.
Therefore we return the DDR training/initialization success to the
upper layer in order to be able to retry with different settings if
necessary.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Diffstat (limited to 'drivers/ddr/imx/imx8m/ddrphy_train.c')
| -rw-r--r-- | drivers/ddr/imx/imx8m/ddrphy_train.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/ddr/imx/imx8m/ddrphy_train.c b/drivers/ddr/imx/imx8m/ddrphy_train.c index 18f7ed7fea9..306af82504f 100644 --- a/drivers/ddr/imx/imx8m/ddrphy_train.c +++ b/drivers/ddr/imx/imx8m/ddrphy_train.c @@ -8,13 +8,14 @@ #include <asm/arch/ddr.h> #include <asm/arch/lpddr4_define.h> -void ddr_cfg_phy(struct dram_timing_info *dram_timing) +int ddr_cfg_phy(struct dram_timing_info *dram_timing) { struct dram_cfg_param *dram_cfg; struct dram_fsp_msg *fsp_msg; unsigned int num; int i = 0; int j = 0; + int ret; /* initialize PHY configuration */ dram_cfg = dram_timing->ddrphy_cfg; @@ -60,7 +61,9 @@ void ddr_cfg_phy(struct dram_timing_info *dram_timing) dwc_ddrphy_apb_wr(0xd0099, 0x0); /* Wait for the training firmware to complete */ - wait_ddrphy_training_complete(); + ret = wait_ddrphy_training_complete(); + if (ret) + return ret; /* Halt the microcontroller. */ dwc_ddrphy_apb_wr(0xd0099, 0x1); @@ -83,4 +86,6 @@ void ddr_cfg_phy(struct dram_timing_info *dram_timing) /* save the ddr PHY trained CSR in memory for low power use */ ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num); + + return 0; } |