diff options
| author | Tom Rini <trini@konsulko.com> | 2020-01-07 08:45:43 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-01-07 08:45:43 -0500 |
| commit | d8a3f5259a36e76d1de127f65714c40918e8ee4c (patch) | |
| tree | 6a4ca1942f084a11465ad990433306c2dfdc7b55 /drivers/ddr/imx/imx8m/ddrphy_train.c | |
| parent | ac0f978afd4b8d388b0b194bc6e5982efc383a59 (diff) | |
| parent | b6e7ef4bf71bc0927dea35fdec0a653a82ae57a7 (diff) | |
Merge tag 'u-boot-imx-20200107' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
New for 2020.04
---------------
- New boards
Embedded Artists COM board
Xea Board
- Switch to DM:
Aristainetos boards
Toradex colibri (DM_ETH)
iCubox
GE bx50v3
mx7dsabre (DM_ETH)
cx9020
- New features:
Bootaux with elf files
Default SYS_THUMB_BUILD for i.MX6/7
- Fixes:
DHCOM i.MX6 PDK
Engicam
i.MX8M tools (imx8m_image)
Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
Diffstat (limited to 'drivers/ddr/imx/imx8m/ddrphy_train.c')
| -rw-r--r-- | drivers/ddr/imx/imx8m/ddrphy_train.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/ddr/imx/imx8m/ddrphy_train.c b/drivers/ddr/imx/imx8m/ddrphy_train.c index 18f7ed7fea9..306af82504f 100644 --- a/drivers/ddr/imx/imx8m/ddrphy_train.c +++ b/drivers/ddr/imx/imx8m/ddrphy_train.c @@ -8,13 +8,14 @@ #include <asm/arch/ddr.h> #include <asm/arch/lpddr4_define.h> -void ddr_cfg_phy(struct dram_timing_info *dram_timing) +int ddr_cfg_phy(struct dram_timing_info *dram_timing) { struct dram_cfg_param *dram_cfg; struct dram_fsp_msg *fsp_msg; unsigned int num; int i = 0; int j = 0; + int ret; /* initialize PHY configuration */ dram_cfg = dram_timing->ddrphy_cfg; @@ -60,7 +61,9 @@ void ddr_cfg_phy(struct dram_timing_info *dram_timing) dwc_ddrphy_apb_wr(0xd0099, 0x0); /* Wait for the training firmware to complete */ - wait_ddrphy_training_complete(); + ret = wait_ddrphy_training_complete(); + if (ret) + return ret; /* Halt the microcontroller. */ dwc_ddrphy_apb_wr(0xd0099, 0x1); @@ -83,4 +86,6 @@ void ddr_cfg_phy(struct dram_timing_info *dram_timing) /* save the ddr PHY trained CSR in memory for low power use */ ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num); + + return 0; } |