diff options
| author | Tom Rini <trini@konsulko.com> | 2019-10-09 09:35:43 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-10-09 11:44:45 -0400 |
| commit | eaa0bde05186b1738d221bc5effc6f257a14e360 (patch) | |
| tree | 4e3c589df0fcd55fb38587ff708f6cd4a0d3863b /drivers/ddr/imx/imx8m/helper.c | |
| parent | 8c05abad1367e33908ee43c590801e338967838d (diff) | |
| parent | 9fb50c68daa696056c7842989e5f7fae1d326b34 (diff) | |
Merge tag 'u-boot-imx-20191009' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20191009
-------------------
Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/595148532
- MX6UL / ULZ
- Toradex board
- Allow to set OCRAM for MX6Q/D
- MX7ULP
- MX8: (container image, imx8mq_mek), SCU API
- fix several board booting from SD/EMMC (cubox-i for example)
- pico boards
[trini: display5 merged manually]
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'drivers/ddr/imx/imx8m/helper.c')
| -rw-r--r-- | drivers/ddr/imx/imx8m/helper.c | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/imx8m/helper.c index 61cd4f6db12..b3e63834ca8 100644 --- a/drivers/ddr/imx/imx8m/helper.c +++ b/drivers/ddr/imx/imx8m/helper.c @@ -31,7 +31,17 @@ void ddr_load_train_firmware(enum fw_type type) unsigned long pr_to32, pr_from32; unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0; unsigned long imem_start = (unsigned long)&_end + fw_offset; - unsigned long dmem_start = imem_start + IMEM_LEN; + unsigned long dmem_start; + +#ifdef CONFIG_SPL_OF_CONTROL + if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) { + imem_start = roundup((unsigned long)&_end + + fdt_totalsize(gd->fdt_blob), 4) + + fw_offset; + } +#endif + + dmem_start = imem_start + IMEM_LEN; pr_from32 = imem_start; pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; @@ -57,7 +67,7 @@ void ddr_load_train_firmware(enum fw_type type) i += 4; } - debug("check ddr4_pmu_train_imem code\n"); + debug("check ddr_pmu_train_imem code\n"); pr_from32 = imem_start; pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; for (i = 0x0; i < IMEM_LEN; ) { @@ -74,9 +84,9 @@ void ddr_load_train_firmware(enum fw_type type) i += 4; } if (error) - printf("check ddr4_pmu_train_imem code fail=%d\n", error); + printf("check ddr_pmu_train_imem code fail=%d\n", error); else - debug("check ddr4_pmu_train_imem code pass\n"); + debug("check ddr_pmu_train_imem code pass\n"); debug("check ddr4_pmu_train_dmem code\n"); pr_from32 = dmem_start; @@ -95,9 +105,9 @@ void ddr_load_train_firmware(enum fw_type type) } if (error) - printf("check ddr4_pmu_train_dmem code fail=%d", error); + printf("check ddr_pmu_train_dmem code fail=%d", error); else - debug("check ddr4_pmu_train_dmem code pass\n"); + debug("check ddr_pmu_train_dmem code pass\n"); } void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, |