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author | Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> | 2025-07-07 10:07:38 +0530 |
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committer | Michal Simek <michal.simek@amd.com> | 2025-07-08 14:58:44 +0200 |
commit | 7d8eafcf98e3fbc6df6d423c6d35c42af67b5e93 (patch) | |
tree | 7a25e3df822581eb8253ec968821b46e5dd1ad7e /drivers/ddr/imx/imx8ulp/ddr_init.c | |
parent | f289c36f074dc24d8ed10e80180ffde4214b6be8 (diff) |
xilinx: zynqmp: disable CONFIG_SPI_FLASH_BAR
Legacy SPI flash devices used a 24-bit (3-byte) addressing scheme,
limiting the addressable memory to 16 MB. To support larger densities
(256 Mbit and higher), extended addressing schemes, such as 32-bit
(4-byte) addressing, were introduced. If the flash density exceeds
16 MB and CONFIG_SPI_FLASH_BAR is disabled, the device will use a
4-byte addressing mode.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250707043738.795179-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'drivers/ddr/imx/imx8ulp/ddr_init.c')
0 files changed, 0 insertions, 0 deletions