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authorAndre Przywara <andre.przywara@arm.com>2022-12-02 21:48:19 +0000
committerAndre Przywara <andre.przywara@arm.com>2023-10-22 23:41:51 +0100
commita94c9c809b26c9fbc58dcc2796ff879fc56b0c7e (patch)
treee8b1b9d98323b3d60daae37e1dd49ca3eea37ee8 /drivers/ddr/imx/imx8ulp
parent39ba474698bb4bc3dc48fd0c024f7cf06b08077a (diff)
sunxi: clock: support D1/R528 PLL6 clock
The PLL_PERIPH0 clock changed a bit in the D1/R528/T113s SoCs: there is new P0 divider at bits [18:16], and the M divider is 1. Add code to support this version of "PLL6". Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'drivers/ddr/imx/imx8ulp')
0 files changed, 0 insertions, 0 deletions