diff options
| author | Michal Simek <michal.simek@amd.com> | 2024-04-16 08:55:15 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-04-22 11:01:48 -0600 |
| commit | d20bcbaa65cee879510ed4e96e45fa101bea6f5a (patch) | |
| tree | 8c8710f0f29007f50377f581df78759ba014d2f7 /drivers/ddr/imx/imx8ulp | |
| parent | 6e316e3f397b5e01e98c5dd56cdbaab961daeedf (diff) | |
Kconfig: Remove trailing whitespace in its prompt
All errors are generated by ./tools/qconfig.py -b -j8 -i whatever.
Error look like this:
warning: SPL_CLK_CCF (defined at drivers/clk/Kconfig:59) has leading or
trailing whitespace in its prompt
Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'drivers/ddr/imx/imx8ulp')
| -rw-r--r-- | drivers/ddr/imx/imx8ulp/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ddr/imx/imx8ulp/Kconfig b/drivers/ddr/imx/imx8ulp/Kconfig index 5448c33838c..005f581f4ba 100644 --- a/drivers/ddr/imx/imx8ulp/Kconfig +++ b/drivers/ddr/imx/imx8ulp/Kconfig @@ -5,7 +5,7 @@ config IMX8ULP_DRAM bool "imx8m dram" config IMX8ULP_DRAM_PHY_PLL_BYPASS - bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK " + bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK" depends on IMX8ULP_DRAM config SAVED_DRAM_TIMING_BASE |