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authorWeijie Gao <weijie.gao@mediatek.com>2024-12-17 16:39:16 +0800
committerTom Rini <trini@konsulko.com>2024-12-31 10:58:52 -0600
commit6e45549f4dac42748d66462e04f940ef6737289d (patch)
treeb26eba1216b3f46c633331048d27588a1739053c /drivers/ddr/imx/phy/ddrphy_train.c
parent25fb58e88aba0c4af0af554d7b141be3f2e5e0b5 (diff)
clk: mediatek: mt7629: fix parent clock of some top clock muxes
According to the mt7629 programming guide, the CLK_TOP_F10M_REF_SEL shares the same parent selection with CLK_TOP_IRRX_SEL, while the present parent selection for CLK_TOP_F10M_REF_SEL is actually used for CLK_TOP_SGMII_REF_1_SEL. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Diffstat (limited to 'drivers/ddr/imx/phy/ddrphy_train.c')
0 files changed, 0 insertions, 0 deletions