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| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2024-01-23 19:16:20 +0200 |
|---|---|---|
| committer | Anatolij Gustschin <agust@denx.de> | 2024-04-21 09:07:01 +0200 |
| commit | 97b6914e2b125ae47ae6711cb0975a18b75c1634 (patch) | |
| tree | 48832d610d61ee6e3a029ae66083c63ac7ef7dc5 /drivers/ddr/imx/phy/ddrphy_train.c | |
| parent | b9ef623c1145c3897deef009c860c0576bc6a310 (diff) | |
video: tegra20: dc: add PLLD2 parent support
T30+ SOC have second PLLD - PLLD2 which can be actively used by
DC and act as main DISP1/2 clock parent.
Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565
Tested-by: Ion Agorria <ion@agorria.com> # HTC One X
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/ddr/imx/phy/ddrphy_train.c')
0 files changed, 0 insertions, 0 deletions