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| author | Christian Marangi <ansuelsmth@gmail.com> | 2024-08-03 10:43:23 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-08-19 16:15:26 -0600 |
| commit | a942c0c3f5d454241cf2c1d61d06a42dcd6a14cc (patch) | |
| tree | a3a1f15b0b516f487ec929908cc501f4939d1626 /drivers/ddr/imx/phy/ddrphy_train.c | |
| parent | 6dfa991204a6fe033a5f0c49ff4f1d6e8af3ed7c (diff) | |
clk: mediatek: mt7622: add missing clock MUX1_SEL
Add missing infra clock MUX1_SEL needed for CPU clock. This is needed to
match the upstream clk ID order in preparation for OF_UPSTREAM.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Diffstat (limited to 'drivers/ddr/imx/phy/ddrphy_train.c')
0 files changed, 0 insertions, 0 deletions