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authorJonas Karlman <jonas@kwiboo.se>2023-03-14 00:38:32 +0000
committerKever Yang <kever.yang@rock-chips.com>2023-03-19 13:20:21 +0800
commitd11f0dac30215361aa046f593d003a7ea094e8a1 (patch)
tree4854f66a0324e573f51bebb72b2cb170d2728c98 /drivers/ddr/imx/phy/ddrphy_train.c
parent42a502ad1ae23b923dfcf8c5caa0aa727efd4062 (diff)
mmc: rockchip_dw_mmc: Fix get_mmc_clk return value
The get_mmc_clk ops is expected to set a clock rate and return the configured rate as an unsigned value. However, if clk_set_rate fails, e.g. using a fixed rate clock, a negative error value is returned. The mmc core will treat this as a valid unsigned rate and tries to configure a divider based on this bogus clock rate. Use 0 as the return value when setting clock rate fails, the mmc core will configure to use bypass mode instead of using a bogus divider. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/ddr/imx/phy/ddrphy_train.c')
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