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authorAniket Limaye <a-limaye@ti.com>2024-11-19 06:02:58 +0530
committerTom Rini <trini@konsulko.com>2024-12-04 14:30:18 -0600
commit82ab094c1a2579ab7fa073460ec1a524c253f126 (patch)
tree1f7870da5ab4499b66a370c97d45a25873cb8ba1 /drivers/ddr/imx/phy/ddrphy_utils.c
parentafe0ab6d3004b435cd17d3b5864de6461d68c7a0 (diff)
arm: mach-k3: j721e-init.c: Add support for CONFIG_K3_OPP_LOW
The default j7200 devicetree and k3_avs driver set 2GHz/1GHz frequency for A72/MSMC clks and the OPP_NOM voltage. J7200 SOCs may support OPP_LOW Operating Performance Point: 1GHz/500MHz clks for A72/MSMC and OPP_LOW AVS voltage read from efuse. Hence, add a config check in board_init_f() to select OPP_LOW specs: - Check if OPP_LOW AVS voltage read from efuse is valid. - Use the device IDs and clock IDs (TISCI docs [0]) to find the A72 and MSMC clock frequencies in the devicetree. - Fixup the clock frequencies in devicetree as per OPP_LOW spec. k3_avs driver programs the OPP_LOW AVS voltage for VDD_CPU through k3_avs_notify_freq() callback from clk_k3. [0]: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html Signed-off-by: Aniket Limaye <a-limaye@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Diffstat (limited to 'drivers/ddr/imx/phy/ddrphy_utils.c')
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