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authorSean Anderson <seanga2@gmail.com>2023-11-04 16:37:44 -0400
committerTom Rini <trini@konsulko.com>2023-11-16 12:43:48 -0500
commit38ef64e6ce3d1f84478c6d2700e4d76f80cfcaf4 (patch)
tree4b390e237ef5d64a318e6381c570291c5e45bb3e /drivers/ddr/imx/phy/helper.c
parent57d3da6fee1d4d8691a74d9b7bb5b7bc0d4e4e63 (diff)
spl: nand: Set bl_len to page size
Since commit 34793598c83 ("mtd: nand: mxs_nand_spl: Remove the page aligned access") there are no longer any users of nand_get_mtd. However, it is still important to know what the page size is so we can allocate a large-enough buffer. If the image size is not page-aligned, we will go off the end of the buffer and clobber some memory. Introduce a new function nand_page_size which returns the page size. For most drivers it is easy to determine the page size. However, a few need to be modified since they only keep the page size around temporarily. It's possible that this patch could cause a regression on some platforms if the offset is non-aligned and there is invalid address space immediately before the load address. spl_load_legacy_img does not (except when compressing) respect bl_len, so only boards with SPL_LOAD_FIT (8 boards) or SPL_LOAD_IMX_CONTAINER (none in tree) would be affected. defconfig CONFIG_TEXT_BASE ======================= ================ am335x_evm 0x80800000 am43xx_evm 0x80800000 am43xx_evm_rtconly 0x80800000 am43xx_evm_usbhost_boot 0x80800000 am43xx_hs_evm 0x80800000 dra7xx_evm 0x80800000 gwventana_nand 0x17800000 imx8mn_bsh_smm_s2 0x40200000 All the sitara boards have DDR mapped at 0x80000000. gwventana is an i.MX6Q which has DDR at 0x10000000. I don't have the IMX8MNRM handy, but on the i.MX8M DDR starts at 0x40000000. Therefore all of these boards can handle a little underflow. Signed-off-by: Sean Anderson <seanga2@gmail.com>
Diffstat (limited to 'drivers/ddr/imx/phy/helper.c')
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