diff options
| author | Tom Rini <trini@konsulko.com> | 2024-12-23 09:42:18 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-12-23 10:28:15 -0600 |
| commit | 68736cf8e313b74db6a6d32cbd081d1a42dbc021 (patch) | |
| tree | 79c367b3a9845511dbb3a269815c1b3402876b4b /drivers/ddr/imx/phy/helper.c | |
| parent | 5947cd76acdd65f48f0748af01241cb6c0756fba (diff) | |
| parent | 6016960ceb9d3fda591cda94df3841748fb65596 (diff) | |
Merge tag 'u-boot-imx-next-20241223' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/23987
- imx8m: Remove global ddrphy_trained_csr as it is a per board
configuration.
- Add DM_FLAG_ACTIVE_DMA flag for FEC network driver to avoid potential
kernel crash.
- Miscellaneous improvements for i.MX8M Venice Gateworks platforms.
Diffstat (limited to 'drivers/ddr/imx/phy/helper.c')
| -rw-r--r-- | drivers/ddr/imx/phy/helper.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/ddr/imx/phy/helper.c b/drivers/ddr/imx/phy/helper.c index c1fc800f191..b0dfc3a0b4f 100644 --- a/drivers/ddr/imx/phy/helper.c +++ b/drivers/ddr/imx/phy/helper.c @@ -181,7 +181,7 @@ void *dram_config_save(struct dram_timing_info *timing_info, unsigned long saved saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num; saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num; - saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num; + saved_timing->ddrphy_trained_csr_num = timing_info->ddrphy_trained_csr_num; saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num; /* save the fsp table */ @@ -209,9 +209,9 @@ void *dram_config_save(struct dram_timing_info *timing_info, unsigned long saved /* save the ddrphy csr */ saved_timing->ddrphy_trained_csr = cfg; - for (i = 0; i < ddrphy_trained_csr_num; i++) { - cfg->reg = ddrphy_trained_csr[i].reg; - cfg->val = ddrphy_trained_csr[i].val; + for (i = 0; i < timing_info->ddrphy_trained_csr_num; i++) { + cfg->reg = timing_info->ddrphy_trained_csr[i].reg; + cfg->val = timing_info->ddrphy_trained_csr[i].val; cfg++; } |