ARM: mvebu: a38x: sync ddr training code with upstream

This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.

The upstream code is incorporated omitting the ddr4 and apn806 and
folding the nested a38x directory up one level. After that a
semi-automated step is used to drop unused features with unifdef

  find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
    xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
		-UCONFIG_APN806 -UCONFIG_MC_STATIC \
		-UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
		-UCONFIG_64BIT

INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE.

Some now empty files are removed and the ternary license is replaced
with a SPDX GPL-2.0+ identifier.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

1 files changed, 0 insertions, 48 deletions

diff --git a/drivers/ddr/marvell/a38x/ddr3_hws_hw_training.h b/drivers/ddr/marvell/a38x/ddr3_hws_hw_training.h
deleted file mode 100644
index 55bc0d286a9..00000000000
--- a/drivers/ddr/marvell/a38x/ddr3_hws_hw_training.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) Marvell International Ltd. and its affiliates
- */
-
-#ifndef _DDR3_HWS_HW_TRAINING_H
-#define _DDR3_HWS_HW_TRAINING_H
-
-/* struct used for DLB configuration array */
-struct dlb_config {
-	u32 reg_addr;
-	u32 reg_data;
-};
-
-/* Topology update structure */
-struct topology_update_info {
-	int	update_ecc;
-	u8	ecc;
-	int	update_width;
-	u8	width;
-	int	update_ecc_pup3_mode;
-	u8	ecc_pup_mode_offset;
-};
-
-/* Topology update defines */
-#define TOPOLOGY_UPDATE_WIDTH_16BIT		1
-#define TOPOLOGY_UPDATE_WIDTH_32BIT		0
-#define TOPOLOGY_UPDATE_WIDTH_32BIT_MASK	0xf
-#define TOPOLOGY_UPDATE_WIDTH_16BIT_MASK	0x3
-
-#define TOPOLOGY_UPDATE_ECC_ON			1
-#define TOPOLOGY_UPDATE_ECC_OFF			0
-#define TOPOLOGY_UPDATE_ECC_OFFSET_PUP4		4
-#define TOPOLOGY_UPDATE_ECC_OFFSET_PUP3		3
-
-/*
- * 1. L2 filter should be set at binary header to 0xd000000,
- *    to avoid conflict with internal register IO.
- * 2. U-Boot modifies internal registers base to 0xf100000,
- *    and than should update L2 filter accordingly to 0xf000000 (3.75 GB)
- */
-/* temporary limit l2 filter to 3GiB (LSP issue) */
-#define L2_FILTER_FOR_MAX_MEMORY_SIZE 0xc0000000
-#define ADDRESS_FILTERING_END_REGISTER 0x8c04
-
-#define SUB_VERSION	0
-
-#endif /* _DDR3_HWS_HW_TRAINING_H */