diff options
| author | Tom Rini <trini@konsulko.com> | 2022-01-14 10:43:14 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-01-14 10:43:14 -0500 |
| commit | 9b72d934c2f7d8ee894f87e082577743877eb76e (patch) | |
| tree | 875f11c867129e7550c7e86ae672052b8b0612a8 /drivers/ddr/marvell/a38x/ddr3_training_centralization.c | |
| parent | 25711b07ca1dcf73dc41b45ca040dadbcff0fa08 (diff) | |
| parent | 1dcbcc715e87da6d30b8ae22f1ef04c881cfea5b (diff) | |
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- mvebu: Move PCIe code from serdes to PCIe driver (Pali)
- mtd: nand: pxa3xx: use marvell, prefix for custom DT properties
(Pierre)
- Add PCIe support for Iomega iConnect board (Tony)
- ddr: marvell: a38x: Misc improvements / fixes (Marek)
- tools: kwbimage: Load address fixes (Pali)
- mvebu: db-88f6720: Fix CONFIG_SPL_TEXT_BASE and remove wrong memory
layout (Pali)
- mvebu: Replace hardcoded values 0x0030/0x4030 by proper calculation
(Pali)
Diffstat (limited to 'drivers/ddr/marvell/a38x/ddr3_training_centralization.c')
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training_centralization.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c index 648b37ef6f7..42308b6965d 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c @@ -55,6 +55,7 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode) enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM]; u32 if_id, pattern_id, bit_id; u8 bus_id; + u8 current_byte_status; u8 cur_start_win[BUS_WIDTH_IN_BITS]; u8 centralization_result[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS]; u8 cur_end_win[BUS_WIDTH_IN_BITS]; @@ -166,6 +167,10 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode) result[search_dir_id][7])); } + current_byte_status = + mv_ddr_tip_sub_phy_byte_status_get(if_id, + bus_id); + for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS; bit_id++) { /* check if this code is valid for 2 edge, probably not :( */ @@ -174,11 +179,32 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode) [HWS_LOW2HIGH] [bit_id], EDGE_1); + if (current_byte_status & + BYTE_SPLIT_OUT_MIX) { + if (cur_start_win[bit_id] >= 64) + cur_start_win[bit_id] -= 64; + else + cur_start_win[bit_id] = 0; + DEBUG_CENTRALIZATION_ENGINE + (DEBUG_LEVEL_INFO, + ("pattern %d IF %d pup %d bit %d subtract 64 adll from start\n", + pattern_id, if_id, bus_id, bit_id)); + } cur_end_win[bit_id] = GET_TAP_RESULT(result [HWS_HIGH2LOW] [bit_id], EDGE_1); + if (cur_end_win[bit_id] >= 64 && + (current_byte_status & + BYTE_SPLIT_OUT_MIX)) { + cur_end_win[bit_id] -= 64; + DEBUG_CENTRALIZATION_ENGINE + (DEBUG_LEVEL_INFO, + ("pattern %d IF %d pup %d bit %d subtract 64 adll from end\n", + pattern_id, if_id, bus_id, bit_id)); + } + /* window length */ current_window[bit_id] = cur_end_win[bit_id] - |