ddr: marvell: a38x: Add support for DDR4 from Marvell mv-ddr-marvell repository

This syncs drivers/ddr/marvell/a38x/ with the master branch of repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git

up to the commit "mv_ddr: a3700: Use the right size for memset to not overflow"
d5acc10c287e40cc2feeb28710b92e45c93c702c

This patch was created by following steps:

	1. Replace all a38x files in U-Boot tree by files from upstream github
	Marvell mv-ddr-marvell repository.

	2. Run following command to omit portions not relevant for a38x, ddr3, and ddr4:

	files=drivers/ddr/marvell/a38x/*
	unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_APN806 \
		-UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
		-UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \
		-UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DCONFIG_ARMADA_38X -UCONFIG_ARMADA_39X \
		-UCONFIG_64BIT $files

	3. Manually change license to SPDX-License-Identifier
	(upstream license in  upstream github repository contains long license
	texts and U-Boot is using just SPDX-License-Identifier.

After applying this patch, a38x, ddr3, and ddr4 code in upstream Marvell github
repository and in U-Boot would be fully identical. So in future applying
above steps could be used to sync code again.

The only change in this patch are:
	1. Some fixes with include files.
	2. Some function return and basic type defines changes in
	mv_ddr_plat.c (to correct Marvell bug).
	3. Remove of dead code in newly copied files (as a result of the
	filter script stripping out everything other than a38x, dd3, and ddr4).

Reference:
    "ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository"
    https://source.denx.de/u-boot/u-boot/-/commit/107c3391b95bcc2ba09a876da4fa0c31b6c1e460

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>

1 files changed, 17 insertions, 0 deletions

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip.h b/drivers/ddr/marvell/a38x/ddr3_training_ip.h
index 056c21497c8..37d21f2b2b4 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip.h
@@ -42,6 +42,13 @@
 #define WRITE_LEVELING_LF_MASK_BIT	0x02000000
 
 /* DDR4 Specific Training Mask bits */
+#if defined (CONFIG_DDR4)
+#define RECEIVER_CALIBRATION_MASK_BIT	0x04000000
+#define WL_PHASE_CORRECTION_MASK_BIT	0x08000000
+#define DQ_VREF_CALIBRATION_MASK_BIT	0x10000000
+#define DQ_MAPPING_MASK_BIT		0x20000000
+#define DM_TUNING_MASK_BIT		0x40000000
+#endif /* CONFIG_DDR4 */
 
 enum hws_result {
 	TEST_FAILED = 0,
@@ -63,6 +70,9 @@ enum auto_tune_stage {
 	WRITE_LEVELING,
 	LOAD_PATTERN_2,
 	READ_LEVELING,
+#if defined(CONFIG_DDR4)
+	SW_READ_LEVELING,
+#endif /* CONFIG_DDR4 */
 	WRITE_LEVELING_SUPP,
 	PBS_RX,
 	PBS_TX,
@@ -78,6 +88,13 @@ enum auto_tune_stage {
 	TX_EMPHASIS,
 	LOAD_PATTERN_HIGH,
 	PER_BIT_READ_LEVELING_TF,
+#if defined(CONFIG_DDR4)
+	RECEIVER_CALIBRATION,
+	WL_PHASE_CORRECTION,
+	DQ_VREF_CALIBRATION,
+	DM_TUNING,
+	DQ_MAPPING,
+#endif /* CONFIG_DDR4 */
 	WRITE_LEVELING_LF,
 	MAX_STAGE_LIMIT
 };