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| author | Neil Armstrong <neil.armstrong@linaro.org> | 2024-04-04 18:46:38 +0200 |
|---|---|---|
| committer | Caleb Connolly <caleb.connolly@linaro.org> | 2024-04-23 13:29:10 +0200 |
| commit | 458123ca626ec07021948f68180bcbaf00a33793 (patch) | |
| tree | aff4d96cc5be9ad99024f0efcc49ffba1abff5c2 /drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c | |
| parent | f0a08d44594a2a6f28763ccd7826bbd39ce63629 (diff) | |
clk: qcom: Add SM8550 clock driver
Add the GCC and TCSRCC clock driver for the SM8550 SoC.
The GCC driver uses the clk-qcom infrastructure to support GDSCs,
Resets and gates. While the TCSRCC is a simpler clock driver which
only supports gates.
The GCC enable and set_rate callbacks contains some tweaks to
setup clocks for Debug UART, SDCard controller and USB.
The TCSRCC gates returns the XO frequency, which is used by the
Synopsys eUSB2 driver to determine the PHY configuration.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Diffstat (limited to 'drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c')
0 files changed, 0 insertions, 0 deletions