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authorSimon Glass <sjg@chromium.org>2023-01-07 14:57:30 -0700
committerSimon Glass <sjg@chromium.org>2023-01-18 11:49:13 -0700
commitb2412dd5dee36cef233053a66f0e0035bc30d44a (patch)
tree02d509c2620b5ce9cf4b2f4469792503ab81f6b0 /drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
parent12619d4ec8a3177d1197117302762bf9e8d03be9 (diff)
rockchip: Enable bootstage on rockpro64
This board is useful for benchmarking overall U-Boot performance. Enable the bootstage feature so we get a report. Since this returns to the boot rom before finishing executing board_init_r() in SPL, add a few bootstage calls so that we can collect timing from TPL. For the stash region, use a portion of SRAM, 64KB below the stack top. This allows the TPL image to be up to nearly 120KB (it is typically about 64KB). SPL normally runs from SDRAM at 0, so can use the same stash region. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c')
0 files changed, 0 insertions, 0 deletions