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| author | Marek Vasut <marek.vasut+renesas@gmail.com> | 2021-04-27 19:52:53 +0200 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2021-06-24 20:22:17 +0200 |
| commit | 44c78aa7ac0f4b22491350278f0dd77585416248 (patch) | |
| tree | ad81fad00ca9ee6e4a872f8dc20873402aabbca3 /drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h | |
| parent | fcf3981161140d265b873a5b609b8867328dc9dc (diff) | |
clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code
On R8A779A0 V3U SoC, PLL1 and PLL5 use a divider value
from cpg_pll_configs table while PLL{20,21,30,31,4} use
different control offset. Introduce new types to handle
this and handle those types in the Gen3 clock code.
Based on "clk: renesas: Add support for R8A779A0 V3U PLLn"
by Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Diffstat (limited to 'drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h')
0 files changed, 0 insertions, 0 deletions