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| author | Marek Vasut <marek.vasut+renesas@mailbox.org> | 2023-09-17 16:11:37 +0200 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@mailbox.org> | 2023-10-01 00:08:28 +0200 |
| commit | 47ce17386bbeffe8f307b8902f6f8f3ebca67467 (patch) | |
| tree | 0f7e5858e1e7e3f1d2e583c4946a3b2b9018481f /drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h | |
| parent | 79d4ef4b472912b744e547b843cdddd2351574b2 (diff) | |
clk: renesas: Synchronize R8A779G0 V4H clock tables with Linux 6.5.3
Synchronize R-Car R8A779G0 V4H clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
The PLL2_VAR is not implemented yet and PLL2 is still configured
as regular PLL2 only.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Diffstat (limited to 'drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h')
0 files changed, 0 insertions, 0 deletions