diff options
| author | Tom Rini <trini@konsulko.com> | 2021-07-07 13:32:22 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-07-07 13:32:22 -0400 |
| commit | 5b8a83551d339736af92c43524ed0e1ba01122af (patch) | |
| tree | c05ddf8c68a2c7f00c8843a231026d95b3d82f43 /drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h | |
| parent | 54fb6e396dd6a0cfbbed77d6baffa23899f4fca9 (diff) | |
| parent | 7bb1cc3bb9d6fca5f285db4df2299c3b80aa8c4a (diff) | |
Merge branch '2021-07-06-update-to-gcc11-clang11'
- Update CI to use gcc-11.1 and clang-11 to build everything. This
requires a few fixes to the code that these newer compilers have
exposed.
Diffstat (limited to 'drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h')
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h index ab152cb455e..55832a55405 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h @@ -8,6 +8,7 @@ #include "ddr3_training_ip.h" #include "ddr3_training_ip_db.h" +#include "mv_ddr_plat.h" #define KILLER_PATTERN_LENGTH 32 #define EXT_ACCESS_BURST_LENGTH 8 @@ -112,9 +113,12 @@ int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type, int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask); int ddr3_tip_write_cs_result(u32 dev_num, u32 offset); int ddr3_tip_reset_fifo_ptr(u32 dev_num); -int ddr3_tip_read_pup_value(u32 dev_num, u32 pup_values[], int reg_addr, u32 mask); -int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr, u32 mask); -int ddr3_tip_write_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr); +int ddr3_tip_read_adll_value(u32 dev_num, + u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], + u32 reg_addr, u32 mask); +int ddr3_tip_write_adll_value(u32 dev_num, + u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], + u32 reg_addr); int ddr3_tip_tune_training_params(u32 dev_num, struct tune_train_params *params); #endif /* _DDR3_TRAINING_IP_FLOW_H_ */ |