diff options
| author | Pratyush Yadav <p.yadav@ti.com> | 2021-06-26 00:47:20 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2021-06-28 12:02:39 +0530 |
| commit | b862765c7c9a64640ce557bc10a10b4f20e8584b (patch) | |
| tree | f4123efd62c01cbad1f3bf11ecdb380a4968ac76 /drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h | |
| parent | 4d40e82663fe5ed8b65242bc28b3faaf838f5dcc (diff) | |
mtd: spi-nor-core: Prepare Read SR and FSR for Octal DTR mode
The xSPI Profile 1.0 table specifies how many dummy cycles and address
bytes are needed for the Read Status Register command in Octal DTR mode.
Use that information to send the correct Read SR command.
Some controllers might have trouble reading just 1 byte in DTR mode. So,
when we are in DTR mode read 2 bytes and discard the second. This shows
no side effects with the two flashes I tested: Micron mt35xu512aba and
Cypress s28hs512t.
Update Read FSR to mimic Read SR because they share the same
characteristics.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h')
0 files changed, 0 insertions, 0 deletions