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| author | Tom Rini <trini@konsulko.com> | 2023-05-08 14:31:04 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-05-08 14:31:04 -0400 |
| commit | 11910550b65e6072b9542d462c0aa93f4ca81836 (patch) | |
| tree | 8308c98ffad76d9693654a28090b03f270a7d250 /drivers/ddr/marvell/a38x/mv_ddr_plat.c | |
| parent | 9876c8c147144db2c120fcc9ffa6de27f6894441 (diff) | |
| parent | f1d33a44ca04fdca241c1d89fd79e2e56c930c7e (diff) | |
Merge branch 'master' into next
Diffstat (limited to 'drivers/ddr/marvell/a38x/mv_ddr_plat.c')
| -rw-r--r-- | drivers/ddr/marvell/a38x/mv_ddr_plat.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c index 6e7949ac72c..8ec9fb0874e 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c @@ -1363,13 +1363,6 @@ int mv_ddr_pre_training_soc_config(const char *ddr_type) DRAM_RESET_MASK_MASKED << DRAM_RESET_MASK_OFFS); } - /* Check if DRAM is already initialized */ - if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & - (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) { - printf("%s Training Sequence - 2nd boot - Skip\n", ddr_type); - return MV_OK; - } - /* Fix read ready phases for all SOC in reg 0x15c8 */ reg_val = reg_read(TRAINING_DBG_3_REG); |