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authorMarek BehĂșn <kabel@kernel.org>2024-06-18 17:34:35 +0200
committerStefan Roese <sr@denx.de>2024-07-08 08:20:58 +0200
commitcae6e8993c8eaed7c520b1046766b658e0f97b90 (patch)
tree55417df27941369a19068050447b7f8b9658956b /drivers/ddr/marvell/a38x/old/ddr3_a38x_topology.h
parent137057ac16b882725f60d12fc2440fdc8530cb3a (diff)
ddr: marvell: a38x: Import old DDR training code from 2017 version of U-Boot
Import DDR training code from commit 1b69ce2fc0ec ("arm: mvebu: ddr3_debug: remove self assignments") into drivers/ddr/marvell/a38x/old/. The code is not used yet. Explanation: Since 2019, on some Turris Omnia boards we have been having problems with newer versions of Marvell's DDR3 training code for Armada 38x, which is ported from mv-ddr-marvell [1] to U-Boot into the drivers/ddr/marvell/a38x/ directory: - sometimes the DDR3 training fails on some older boards, sometime it fails on some newer boards - other times it succeeds, but some boards experience crashes of the operating system after running for some time. Using the stock version of Turris Omnia's U-Boot from solved these issues, but this solution was not satisfactory, since we wanted features from new U-Boot. Back in 2020-2022 we have spent several months trying to debug the issues, working with Marvell, on our own, and also with U-Boot community, but these issues persist still. One solution we used back in 2019 was a "hybrid U-Boot": the SPL part (containing the DDR3 training code) was taken from the stock version, while the proper part was current U-Boot at the time. This solution also has its drawbacks, of which the main one is the need to glue binaries from two separate builds. Since then there have been some more changes to the DDR3 training code in upstream mv-ddr-marvell that have been ported to U-Boot. We have provided our users experimental builds of U-Boot in the TurrisOS so that they could try upgrading the firmware and let us know if those problems still exist. And they do. We do not have the time nor manpower to debug this problem and fix it properly. Marvell was also no able to provide a solution to this, probably because they do not have the manpower as well. I have therefore come up with this "not that pretty" solution: take the DDR3 training code from an older version of U-Boot that is known to work, put it into current U-Boot under old/ subdirectory within drivers/ddr/marvell/a38x/, build into the SPL binary both the old and new versions and make it possible to select the old version via an env variable. [1] https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell Signed-off-by: Marek BehĂșn <kabel@kernel.org>
Diffstat (limited to 'drivers/ddr/marvell/a38x/old/ddr3_a38x_topology.h')
-rw-r--r--drivers/ddr/marvell/a38x/old/ddr3_a38x_topology.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_a38x_topology.h b/drivers/ddr/marvell/a38x/old/ddr3_a38x_topology.h
new file mode 100644
index 00000000000..f27bbff7338
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_a38x_topology.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_A38X_TOPOLOGY_H
+#define _DDR3_A38X_TOPOLOGY_H
+
+#include "ddr_topology_def.h"
+
+/* Bus mask variants */
+#define BUS_MASK_32BIT 0xf
+#define BUS_MASK_32BIT_ECC 0x1f
+#define BUS_MASK_16BIT 0x3
+#define BUS_MASK_16BIT_ECC 0x13
+#define BUS_MASK_16BIT_ECC_PUP3 0xb
+
+#define DYNAMIC_CS_SIZE_CONFIG
+#define DISABLE_L2_FILTERING_DURING_DDR_TRAINING
+
+#endif /* _DDR3_A38X_TOPOLOGY_H */