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authorTom Rini <trini@konsulko.com>2021-03-12 08:00:39 -0500
committerTom Rini <trini@konsulko.com>2021-03-12 08:00:39 -0500
commitad7e1c7c6e2bde2b369f10984d41d6b1833453fb (patch)
treef7bf2fcc1d49c12c45267a4dd9581983445c94d5 /drivers/ddr/marvell/axp/ddr3_dfs.c
parent4c8e9361bb3ced3b20e45ee94b3751da1a9ed850 (diff)
parent15942805b7efe47e186d8b30ec378666561ad1f9 (diff)
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Some more updates/sync's to A38x DDR3 code (Marek & Pali) - marvell/ddr/AXP: Some type fixes found in the LTO work (Marek) - Espressobin: Enable more options (Pali) - pci-aardvark: Implement workaround for the readback value of VEND_ID (Paili)
Diffstat (limited to 'drivers/ddr/marvell/axp/ddr3_dfs.c')
-rw-r--r--drivers/ddr/marvell/axp/ddr3_dfs.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/ddr/marvell/axp/ddr3_dfs.c b/drivers/ddr/marvell/axp/ddr3_dfs.c
index b58c0fe01e5..2a4596680b1 100644
--- a/drivers/ddr/marvell/axp/ddr3_dfs.c
+++ b/drivers/ddr/marvell/axp/ddr3_dfs.c
@@ -42,8 +42,8 @@ extern u8 div_ratio[CLK_VCO][CLK_DDR];
extern void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
#else
extern u16 odt_dynamic[ODT_OPT][MAX_CS];
-extern u8 div_ratio1to1[CLK_CPU][CLK_DDR];
-extern u8 div_ratio2to1[CLK_CPU][CLK_DDR];
+extern u8 div_ratio1to1[CLK_VCO][CLK_DDR];
+extern u8 div_ratio2to1[CLK_VCO][CLK_DDR];
#endif
extern u16 odt_static[ODT_OPT][MAX_CS];