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authorQuentin Schulz <quentin.schulz@theobroma-systems.com>2024-03-14 10:36:26 +0100
committerKever Yang <kever.yang@rock-chips.com>2024-03-14 18:20:04 +0800
commit768636c371482268cb9580f2056ec8a4f8099f96 (patch)
treefa398031485d47e4b4ae763db02de508fa2fda72 /drivers/ddr/marvell/axp/ddr3_dqs.c
parent1fb75f7ee4bb5ec5d0db95f5edbdf1d2531ca378 (diff)
rockchip: jaguar-rk3588: enable SARADC and derivatives
The SARADC is used on Jaguar for multiple things: - channel 0 is used (at runtime) as a BIOS button, - channel 2 is exposed on the Mezzanine connector for customer specific logic, - channel 5 and 6 are used for identification, Since the SARADC requires a vref-supply provided by the RK806 PMIC, its support and the support for its regulators are also enabled. The button, adc, pmic and regulator commands are also enabled for CLI use in U-Boot for debugging and scripting purposes. The RK806 PMIC on Jaguar being routed on the SPI bus, let's enable Rockchip SPI controller driver. Finally, the SARADC channel 1 on Jaguar is hardwired so will never change in the lifetime of a unit, for that reason, disable the Rockchip Download Mode check by setting ROCKCHIP_BOOT_MODE_REG symbol to 0. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Diffstat (limited to 'drivers/ddr/marvell/axp/ddr3_dqs.c')
0 files changed, 0 insertions, 0 deletions