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| author | Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> | 2024-03-06 16:54:41 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-03-19 18:40:46 -0400 |
| commit | c6a13f3d6f074a20680765309280994288c89ad1 (patch) | |
| tree | 8c9e0063418d0b85ff5678db6415a8526fdc7b82 /drivers/ddr/marvell/axp/ddr3_dqs.c | |
| parent | db5c91b69a1a36a6e772524e1dd7e011d7ad0066 (diff) | |
arm64: gic: Add power up sequence for GIC-600
Arm's GIC-600 features a Power Register (GICR_PWRR),
which needs to be programmed to enable redistributor
operation. Power on the redistributor and wait until
the power on state is reflected by checking the bit
GICR_PWRR.RDPD == 0. While running U-Boot in EL3
without enabling this register, GICR_WAKER.ChildrenAsleep
bit is not getting cleared and loops infinitely.
This register(GICR_PWRR) must be programmed to mark the frame
as powered on, before accessing other registers in the frame.
Rest of initialization sequence remains the same.
ARM GIC-600 IP complies with ARM GICv3 architecture.
Enable this config if GIC-600 IP present.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Diffstat (limited to 'drivers/ddr/marvell/axp/ddr3_dqs.c')
0 files changed, 0 insertions, 0 deletions