diff options
| author | Weijie Gao <weijie.gao@mediatek.com> | 2024-12-17 16:39:23 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-12-31 10:58:52 -0600 |
| commit | 0d4d8e6f47ef22ea6b3041b4c0cb27b4ed4bf188 (patch) | |
| tree | 42abfbccbf70c21179e3633c1203818f53f8a080 /drivers/ddr/marvell/axp/ddr3_hw_training.c | |
| parent | ba365c3d23411620d86b5baf621c8f5a4000ab33 (diff) | |
net: mediatek: use correct register field for SGMII speed selection
The register field for SGMII speed selection is a 2-bit field with
value 0 for 1Gbps and 1 for 2.5Gbps (2/3 are reserved).
So it's necessary to set both bits instead of just setting/clearing
only the lower bit.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Diffstat (limited to 'drivers/ddr/marvell/axp/ddr3_hw_training.c')
0 files changed, 0 insertions, 0 deletions