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author | Svyatoslav Ryhel <clamor95@gmail.com> | 2023-07-03 18:06:54 +0300 |
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committer | Svyatoslav Ryhel <clamor95@gmail.com> | 2023-12-19 21:24:11 +0200 |
commit | 1ba80d1b2ce474e0e924bc9c0c1b44d3554204b1 (patch) | |
tree | 927d5d9f7d9908ef42dae037cfdd313d7b1f3f98 /drivers/ddr/marvell/axp/ddr3_init.h | |
parent | c03cd98d1a163666b4addcdd9a34fc0c77dfd0a5 (diff) |
ARM: tegra: clock: support get and set rate for simple PLL
Simple PLL clocks like PLLD2 were omitted since they do not share common
4 register structure with main clocks. Such clocks are containd in simple
PLL group. Only clock_start_pll function supported them. This patch expands
this support on clock_set_rate and clock_get_rate which should make
simple PLL clocks equal to main PLL clocks.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Diffstat (limited to 'drivers/ddr/marvell/axp/ddr3_init.h')
0 files changed, 0 insertions, 0 deletions