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| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2023-11-16 09:35:26 +0200 |
|---|---|---|
| committer | Svyatoslav Ryhel <clamor95@gmail.com> | 2023-12-19 21:24:11 +0200 |
| commit | 944ac34075fe1dd1a16f0dee0d7279c8d49a537a (patch) | |
| tree | 6c488a4a1c1c446416334e3786c6857c9e4a239c /drivers/ddr/marvell/axp/ddr3_init.h | |
| parent | e63ab85dba80f15f6740821a4669569564537f94 (diff) | |
ARM: tegra114: clock: implement PLLD2 support
PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Diffstat (limited to 'drivers/ddr/marvell/axp/ddr3_init.h')
0 files changed, 0 insertions, 0 deletions