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authorJayesh Choudhary <j-choudhary@ti.com>2024-11-26 12:36:12 +0530
committerTom Rini <trini@konsulko.com>2024-12-13 14:11:55 -0600
commit18afd39ef05733b4d320830d06f0c7c9b9c707da (patch)
tree5e326fc694835e287c0246ef2f0b3f5fe52708d4 /drivers/ddr/marvell/axp/ddr3_read_leveling.c
parent0dbf1b35584eeb339e0af5cf10b7df0948d7a42d (diff)
arm: mach-k3: am62p: Add QoS support for DSS
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is done by setting the DSS DMA orderID to greater than 7. DDR intensive software applications can overwhelm the DSS's access to the DDR because of their higher frequency DDR accesses. This can cause flickering in display with certain applications running parallely if the DSS traffic is being serviced through non-RT queue. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Diffstat (limited to 'drivers/ddr/marvell/axp/ddr3_read_leveling.c')
0 files changed, 0 insertions, 0 deletions