clk: ti: clk-k3-pll: Add additional robustness steps to the PLL sequence

Based on the recommendation from HW team make modifications to
the sequence for more robustness.

- Unlock the PLL registers
- Enable external bypass
- Disable the PLL
- Program pllm and pllf
- Program Ref divider
- Enable other PLL controls like DSM_EN, DAC_EN,etc
- Enable calibration if available
- Enable PLL
- Wait for PLL lock and Calibration lock
- Remove external bypass

Re-write the full sequence from scratch as the previous sequence was way
off and keep it in a single commit for bisectability.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>

0 files changed, 0 insertions, 0 deletions