summaryrefslogtreecommitdiff
path: root/drivers/ddr/marvell/axp/ddr3_read_leveling.c
diff options
context:
space:
mode:
authorSam Protsenko <semen.protsenko@linaro.org>2024-03-07 18:04:32 -0600
committerTom Rini <trini@konsulko.com>2024-12-12 14:23:25 -0600
commite5aef1bbf11412eebd4c242b46adff5301353c30 (patch)
treeadd17fdeadcdddc9eb7922c7c09486027812df40 /drivers/ddr/marvell/axp/ddr3_read_leveling.c
parent9bc62c980d418f0a67632ab29cd3501072cdb6f0 (diff)
clk: Propagate clk_set_rate() if CLK_SET_PARENT_RATE present
Sometimes clocks provided to a consumer might not have .set_rate operation (like gate or mux clocks), but have CLK_SET_PARENT_RATE flag set. In that case it's usually possible to find a parent up the tree which is capable of setting the rate (div, pll, etc). Implement a simple lookup procedure for such cases, to traverse the clock tree until .set_rate capable parent is found, and use that parent to actually change the rate. The search will stop once the first .set_rate capable clock is found, which is usually enough to handle most cases. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Diffstat (limited to 'drivers/ddr/marvell/axp/ddr3_read_leveling.c')
0 files changed, 0 insertions, 0 deletions