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| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2023-07-03 18:11:58 +0300 |
|---|---|---|
| committer | Svyatoslav Ryhel <clamor95@gmail.com> | 2023-12-19 21:24:11 +0200 |
| commit | e63ab85dba80f15f6740821a4669569564537f94 (patch) | |
| tree | 079f3d6242b77b5fd0de7f429e559a0a5c55de61 /drivers/ddr/marvell/axp/ddr3_read_leveling.c | |
| parent | 1ba80d1b2ce474e0e924bc9c0c1b44d3554204b1 (diff) | |
ARM: tegra30: clock: implement PLLD2 support
PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Diffstat (limited to 'drivers/ddr/marvell/axp/ddr3_read_leveling.c')
0 files changed, 0 insertions, 0 deletions