diff options
| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2024-04-11 17:29:45 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2024-05-01 22:40:00 +0800 |
| commit | fd55792e143f7ec46c5e70a8683183163d8c6878 (patch) | |
| tree | 445bc82a325414cb4597c6ab1f4f0c775aad3a1f /drivers/ddr/marvell/axp/ddr3_sdram.c | |
| parent | ff0de1f0557ed7d2dab47ba976a37347a1fdc432 (diff) | |
riscv: andesv5: Set default cache line size to 64-bytes
The instruction and data cache line sizes of Andes core
are 64-byte. Select SYS_CACHE_SHIFT_6 for RISCV_NDS so
the SYS_CACHELINE_SIZE is enabled with a default value.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'drivers/ddr/marvell/axp/ddr3_sdram.c')
0 files changed, 0 insertions, 0 deletions