diff options
| author | Simon Glass <sjg@chromium.org> | 2024-06-27 09:29:48 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-06-28 13:54:52 -0600 |
| commit | 37323aec519e5a6e677bb24b11ff141f69533da3 (patch) | |
| tree | 5fb6f9df34d49f586d1500793e888afc876dfd0f /drivers/ddr/marvell/axp/ddr3_write_leveling.c | |
| parent | 024767e66dbe18971e4439b804de96f85462b3e4 (diff) | |
rockchip: bob: kevin: Disable dcache in SPL
This causes a hang, so disable it. Unfortunately the RAM-size fix does
not resolve the problem and I am unsure what is wrong. As soon as the
cache is enabled the board appears to hang.
Fixes: 6d8cdfd1536 ("rockchip: spl: Enable caches to speed up checksum validation")
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/ddr/marvell/axp/ddr3_write_leveling.c')
0 files changed, 0 insertions, 0 deletions