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| author | Tom Rini <trini@konsulko.com> | 2021-08-31 17:52:28 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-08-31 17:55:32 -0400 |
| commit | df6cf3d809fe543651e6bdf133baaa8b9841fe0f (patch) | |
| tree | a884597e97578cb074adc33d3dd961d6675c9879 /drivers/ddr/marvell | |
| parent | a85a8e63c5cf8ccb3905eb5982bf8bdcb2978557 (diff) | |
| parent | b4c2c151b14b59a2403675526adf666710cade67 (diff) | |
Merge branch '2021-08-31-kconfig-migrations-part2' into next
- Further CONFIG to Kconfig migrations
- Some DDR related symbols
- CONFIG_SYS_LOAD_ADDR moved, loadaddr always set in environment now.
- Finish MX7D, convert IMX_CONFIG
- Some RAMBOOT related options
- L1 cache size converted and named consistently for all arches. A
further follow-up to rename things for even better clarity is welcome.
- CONFIG_SKIP_LOWLEVEL_INIT, CONFIG_SYS_MALLOC_LEN
Diffstat (limited to 'drivers/ddr/marvell')
| -rw-r--r-- | drivers/ddr/marvell/axp/ddr3_axp.h | 4 | ||||
| -rw-r--r-- | drivers/ddr/marvell/axp/ddr3_axp_config.h | 4 |
2 files changed, 2 insertions, 6 deletions
diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h index 270691e9bcd..970651f8702 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp.h +++ b/drivers/ddr/marvell/axp/ddr3_axp.h @@ -19,10 +19,10 @@ #define FAR_END_DIMM_ADDR 0x50 #define MAX_DIMM_ADDR 0x60 -#ifndef CONFIG_DDR_FIXED_SIZE +#ifndef CONFIG_SYS_SDRAM_SIZE #define SDRAM_CS_SIZE 0xFFFFFFF #else -#define SDRAM_CS_SIZE (CONFIG_DDR_FIXED_SIZE - 1) +#define SDRAM_CS_SIZE ((CONFIG_SYS_SDRAM_SIZE >> 10) - 1) #endif #define SDRAM_CS_BASE 0x0 #define SDRAM_DIMM_SIZE 0x80000000 diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h index 10d064d0a30..437a02efbac 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_config.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h @@ -16,11 +16,7 @@ * Level 3: Provides the windows margin of each DQ as a results of DQS * centeralization */ -#ifdef CONFIG_DDR_LOG_LEVEL #define DDR3_LOG_LEVEL CONFIG_DDR_LOG_LEVEL -#else -#define DDR3_LOG_LEVEL 0 -#endif #define DDR3_PBS 1 |