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authorCallum Sinclair <callum.sinclair@alliedtelesis.co.nz>2021-08-10 14:51:15 +1200
committerTom Rini <trini@konsulko.com>2021-09-01 19:25:37 -0400
commit223c44904d86a14d6c17e73696186c402e9ba958 (patch)
treefe6e35dc876cde0a0c2da0f6adc060beb254ccb5 /drivers/ddr/microchip/ddr2.c
parent8956854d4839341b61b70aae1f6df53d05084fb2 (diff)
rtc: ds1307: Fix incorrect clock reset for DS13xx
The ds1307 driver also supports the DS1339 and DS1340. However, in ds1307_rtc_reset the register writes assume that the chip is a DS1307. This is evident in the writing of bits SQWE, RS1, RS0 to the control register. While this applies correctly to the DS1307, on a DS1340 the control register doesn't contain those bits (instead, the register is used for clock calibration). By writing these bits the clock calibration will be changed and the chip can become non-functional after a reset call. Signed-off-by: Callum Sinclair <callum.sinclair@alliedtelesis.co.nz>
Diffstat (limited to 'drivers/ddr/microchip/ddr2.c')
0 files changed, 0 insertions, 0 deletions