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| author | Quentin Schulz <quentin.schulz@cherry.de> | 2024-06-06 10:45:34 +0200 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2024-06-14 17:11:29 +0800 |
| commit | aefdec52771694dcaac8bcc6f9772c0b375fc1bd (patch) | |
| tree | 96df1f05ac672c886cfb6d62bf5256a4ff19a34f /drivers/ddr/microchip/ddr2.c | |
| parent | b58e0d304b1896f70ab1ba66a2162d0df9deef6b (diff) | |
rockchip: px30-ringneck: Update SPL_PAD_TO Kconfig option
On px30-ringneck the FIT payload is located at sector 0x200 compared to
the more Rockchip common sector 0x4000 offset:
SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
Because FIT payload is located at sector 0x200 and the TPL+SPL is
located at sector 64, the combined size of TPL+SPL cannot take up more
than 224KiB:
(0x200 - 64) x 512 = 0x38000 (224 KiB)
Adjust SPL_PAD_TO to match the used 0x200 sector offset.
While at it, update the px30-ringneck-u-boot.dtsi to remove the now
unnecessary override of simple-bin:fit:offset since SPL_PAD_TO matches
with the current formula.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Diffstat (limited to 'drivers/ddr/microchip/ddr2.c')
0 files changed, 0 insertions, 0 deletions